1. Field of the Invention
This invention relates to computer timers, and more particularly to a computer controlled mechanism for managing a large number of devices that can measure elapsed time.
2. Description of Related Art
Timers are commonly used in the computer and communications arts to measure the duration in time between events or to indicate when a predetermined amount of time has expired. For example, timers allow a first device to wait a finite amount of time before taking action in response to a failure of a second device to respond as expected. The amount of time that a device waits for a response before considering the second device to have failed is referred to as an "Error Detect Time-Out Value" (EDTOV). In accordance with one common method for implementing a timer, a counter is loaded with a value and decremented at regular intervals by a clock signal. When the value of the counter reaches a predetermined value (such as zero), the timer has expired. This implementation requires that each timer that is concurrently running have a dedicated counter circuit capable of decrementing the value of the timer at each clock cycle.
An alternative method for implementing a timer in systems that have a programmable device (such as a microcontroller or microprocessor) is to have the programmable device load a value into a memory location. The programmable device is then interrupted at regular intervals (either by software instructions embedded in the code being executed or by an external interrupt clock). At each interrupt, the programmable device stops all other functions and decrements the value stored in the memory and checks whether the value is equal to a predetermined value (such as zero). When the value stored is equal to the predetermined value, then the timer has expired.
In some systems in which a great number of events must be timed concurrently, there is a need to maintain a great number of timers to detect the expiration of each EDTOV. Supporting a great number of hardware timers requires many hardware devices (i.e., counters), each of which is dedicated to maintaining and decrementing one EDTOV timer. Alternatively, supporting a great number of software timers requires a substantial amount of software overhead dedicated to decrementing, checking, and signaling the expiration, of each timer.
For example, in systems which communicate in accordance with the well known Fibre Channel protocol, a great number of timers (such as 2,048 8-bit timers) may be desired to be independently maintained at any one time to detect the expiration of an EDTOV related to each of 2,048 exchanges. An exchange is a bi-directional communications session between two devices over the Fibre Channel link. Each of the exchanges comprise a plurality of sequences. Each sequence is a uni-directional communications session comprising a plurality of frames. Frames of data are transmitted at up to 1 Giga-bit per second.
In accordance with the Fibre Channel protocol, action is required if an EDTOV timer associated with any one of the exchanges expires. Furthermore, in accordance with the Fibre Channel protocol, it is desirable for each timer to have a resolution of approximately 1 ms or less. Timers that meet the requirements of the Fibre Channel environment are difficult to implement due to the required resolution, the large number of timers that must be maintained concurrently, and the very fast transfer rate over a Fibre Channel link. Implementing 2,048 software timers at the resolution desired would overburden most controllers, leaving few resources available for any other control functions required to operate the communications link in accordance with the Fibre Channel protocol. Providing a dedicated RISC processor would increase the cost of a Fibre Channel protocol controller. Furthermore, in many cases, even a dedicated RISC processor would be unable to maintain 2,048 timers with a resolution of 1 ms.
For example, assume that 2048 timers must be concurrently managed with a resolution of 1 ms or less in a Fibre Channel system in which data is received at a rate of one word per 38 ns (i.e., 1 Giga-bit/sec.). The smallest Fibre Channel frames are 11 words. Accordingly, a frame may be received or transmitted every 418 ns. Every time a frame is transmitted, a timer must be started, and every time a frame is received a timer must be stopped. The timer accuracy must be maintained concurrently with starting and stopping of the timers. At a RISC processor clock rate of 50 MHz, a start timer operation requires 60 clocks cycles of the RISC processor per timer or 3.1 ms for the all 2048 timers to be started. Each stop timer operation requires 25 RISC processor cycles or 1.3 ms for all 2048 timers. In addition, each timer must be scanned, which requires 1.3 or 25 RISC processor cycles or 1.3 ms for all 2048 timers. It should be clear from these numbers that that firmware cannot manage 2048 timers (at least not at a clock rate of 50 MHz). For example, even if no clocks need to be started, but all 2048 clocks are being maintained, the RISC processor will only be able to update each timer at a rate of once per 3 ms. Since the desired resolution is 1 ms, the RISC must operate at a rate of at least 150 MHz just to maintain the 2048 timers. If the additional burden of starting timers is added, the RISC processor quickly becomes overwhelmed.
Implementing the timers in hardware would require a large number of transistors, and thus increase both the size and cost of the timer within a Fibre Channel interface device.
Accordingly, there is a need for a mechanism which allows a large number of EDTOV timers to be operated concurrently at relatively high resolution without implementing each timer in discrete hardware and without exhausting the processing bandwidth of the controllers which must manage the remainder of a communication protocol.